Generally, a silicon oxide layer may be formed by a chemical vapor deposition (CVD) for electrical insulation between a through-silicon via and a substrate. As a size of the through-silicon via becomes reduced, it may be required to reduce a thickness of an insulating layer formed on a sidewall of the through-silicon via. The insulating layer may also be formed under the through-silicon via. Securing high etch selectivity between the substrate and the insulating layer may be very important in a process that projects the through-silicon via by recessing a bottom surface of the substrate. If the insulating layer is etched during the process of protruding the through-silicon via, the through-silicon via may be exposed. The exposed portion of the through-silicon via may act as a contamination or particle source. As a result, errors in subsequent processes may occur. Thus, it may be desired to improve etching margin of the insulating layer in the process of protruding the through-silicon via.